1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device using a silicon-on-insulator (SOI) structure.
2. Description of Related Art
Semiconductor devices having an SOI structure have become popular accompanying the increased speeds and lower power consumption of semiconductor devices in recent years. In an SOI structure, an insulating layer is formed on a support substrate made of silicon and so forth, and a silicon layer is formed on the insulating layer. In an SOI structure, circuit elements such as transistors are formed on a silicon layer on an insulating layer. Semiconductor devices using an SOI structure have a structure in which the periphery of circuit elements is covered with an insulator. These insulators have lower thermal conductivity than the silicon serving as the support substrate. Consequently, semiconductor devices employing an SOI structure have difficulty in allowing heat generated by a transistor, for example, to escape to the outside, thereby resulting in self-heating. The operation of the transistor becomes unstable if the temperature of the semiconductor device rises due to this self-heating. Consequently, several countermeasures have been devised to deal with this.
Japanese Unexamined Patent Application Publication No. 11-354807 (Shimoida et al.) and Japanese Unexamined Patent Application Publication No. 2004-349537 (Hirano et al.) describe the formation of holes extending from a silicon layer to a support substrate through an insulating layer. In Shimoida et al. and Hirano et al., a material having high thermal conductivity is embedded within these holes. Japanese Unexamined Patent Application Publication No. 2004-72017 (Yoshioka) and Japanese Unexamined Patent Application Publication No. 2000-31487 (Hirasawa et al.) describe the formation of heat-dissipating wires and heat conducting portions extending to upper layer wiring. Yoshioka and Hirasawa et al. disclose technologies which use a conductive layer on a silicon layer to dissipate heat.
However, both Shimoida et al. and Hirano et al. require a process for providing holes in an insulator. Yoshioka and Hirasawa et al. limit the circuit wiring layout due to the presence of a wiring layer and so forth for dissipating heat. In addition, neither of the above technologies consider how heat is to be transferred from a heat generator in the form of a transistor to wiring layers and holes serving as heat dissipators. Consequently, heat dissipation effects become small in the case the thermal resistance from the transistor to the heat dissipator is large.
The following provides an explanation of the relationship between heat generation and heat dissipation of a semiconductor device, and the aforementioned thermal resistance.
When considering the typical relationship between heat absorption and heat generation, a relationship like that expressed by the following equation is valid when Q (W) is taken to represent calorific value, T (° C.) temperature difference, and θ thermal resistance (° C./W).θ=T/Q   (1)
In the case of considering a transistor to be a heat generator, the thermal resistance in the above equation is considered to consist of the thermal resistance θp resulting from a plug between a diffusion layer and a wiring layer, thermal resistance θh of the wiring, thermal resistance θe of an interlayer insulating layer (or package material), and thermal resistance θj of the transistor itself. Therefore, temperature difference T of the above equation is equivalent to the difference between temperature Tj of the diffusion layer and ambient temperature Te of the interlayer insulating layer (or package material). A relationship like that indicated below results when the calorific value Q of the transistor is substituted into the above equation (1).Tj−Te=Q*(θj+θp+θh+θe)   (2)
In this equation (2), Tj and θj are values determined by the structure of the semiconductor device, while Te and θe are values determined by the ambient conditions, package material and package shape. θh is determined by the wiring width and shape, and Yoshioka and Hirasawa et al. disclose technologies for reducing this value of θh.
In other words, in the prior art described above, although θh is reduced to increase heat dissipation effects, there are no considerations whatsoever given to thermal resistance θp extending from a heat generator in the form of the transistor to the wiring. In the case in which this θp ends up becoming large, heat is unable to be propagated from the heat generator in the form of the transistor, thereby resulting in cases in which the aforementioned technologies are unable to adequately increase heat dissipation effects.
Shimoida et al. and Hirano et al. also do not give any consideration whatsoever to the resistance value from a heat generator in the form of a diffusion layer to holes, namely the thermal resistance corresponding to θp. Thus, Shimoida et al. and Hirano et al. required a separate process for forming holes in an insulating layer.
As has been described above, the prior art either required a separate process for providing holes for heat dissipation, or were subject to layout restrictions due to the presence of wiring for heat dissipation. In addition, considerations are not given to thermal resistance from a heat generator to a heat dissipator. Consequently, there were cases in which adequate heat dissipation effects were unable to be obtained.